Job Description

We are seeking a Senior ASIC Verification Engineer with expertise in UVM and SOC verification for a high-visibility project with a leading semiconductor company. This is an onsite hybrid role (3 days/week in Santa Clara, CA) .

Key Responsibilities:

• Develop and execute UVM testbenches for complex ASIC/SOC designs .
• Verify high-speed I/O interfaces (PCIe, USB, Ethernet) and CPU subsystems .
• Collaborate with design teams to debug failures and achieve functional coverage closure .
• Write test plans, develop randomized/directed tests, and use industry-standard tools ( VCS, Xcelium, Verdi ).

Qualifications:

• 10+ years of UVM/SystemVerilog verification experience .
• Strong background in SOC/ASIC verification (CPUs, high-speed I/O, or similar).
• Hands-on experience with Cadence/Synopsys verification tools .
• Bachelor’s or Master’s in Electrical Engineering, Computer Science, or related field .

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